In the current display industry, the liquid crystal display (LCD) has gradually replaced the cathode ray tube (CRT) to become a mainstream product due to its excellent properties of low radiation and low power consumption. In the array structure of LCD, the FFS (Fringe Field Switching) mode is a promising structure owing to its high transmittance, wide viewing angle and low color shift.
Please refer to FIG. 1(a), which shows a top view of the array structure of the FFS mode LCD in the prior art. The FFS mode LCD includes a common electrode 12, a pixel electrode 110, a plurality of gate lines 13, a common line 111, a plurality of data lines 17 and a contact hole 19.
Please refer to FIG. 1(b), which shows a cross-sectional view along A-A line of FIG. 1(a). As shown in FIG. 1(b), the manufacturing steps of the FFS mode LCD are as follows. Firstly, a substrate 11 is provided and the common electrode 12 is formed thereon as shown in FIG. 1(a). Then, a first metal layer is applied on the substrate 11, and the gate lines 13 and the common line 111 are formed simultaneously by etching the first metal layer, wherein the common line 111 directly contacts the common electrode 12 as shown in FIG. 1(c). Subsequently, a gate insulating layer 14 is formed on the substrate 11 and covers the gate lines 13 and the common line 111. Next, a channel portion 15 and a doped portion 16 are formed on the gate insulating layer 14 and correspond to one of the gate lines 13, and a second metal layer covering the whole substrate 11 are sequentially formed on the gate insulating layer 14. The data lines 17, a source electrode 171 and a drain electrode 172 are formed simultaneously by etching the second metal layer. After that, a passivation layer 18 is formed on the data lines 17, the source electrode 171, the drain electrode 172 and a part of the gate insulating layer 14, and covers the whole substrate 11. Then, the passivation layer 18 is etched to form a contact hole 19 on the source electrode 171. Finally, the pixel electrode 110 is formed on the passivation layer 18 and covers the contact hole 19.
The cross-sectional view along B-B line of FIG. 1(a) is shown in FIG. 1(c). As shown in FIG. 1(c), there are two dielectric layers, i.e. the gate insulating layer 14 and the passivation layer 18, interposed between the common electrode 12 and the pixel electrode 110 of the conventional array structure. The common line 111 is interposed between the gate insulating layer 14 and the common electrode 12. The driving voltage becomes unbalanced between the odd (positive) frame and the even (negative) frame due to the thick dielectric layers, which in turn give rise to the image sticking.
From the above description, it is known that how to develop a method for manufacturing the FFS mode LCD with less dielectric layers has become a major problem to be solved. In order to overcome the drawbacks in the prior art, an improved method for manufacturing the FFS mode LCD is provided. The particular design in the present invention not only solves the problems described above, but also is easy to be implemented. Thus, the invention has the utility for the industry.